Managing the power consumption of ICs is an increasingly difficult challenge, because each new generation of portable device includes expanded features and demands longer battery lives.

For a useful primer on circuit design, see Optimize your DSPs for power and performance. To learn how power and performance vary with voltage and temperature, see Push performance and power beyond the ...

A software tool for automatically converting synchronous circuit designs into asynchronous equivalents is being developed by researchers at the University of Edinburgh. Asynchronous ICs – which do not ...

Wire delay is beginning to dominate gate delay in current CMOS technologies. According to Moore’s Law by 2016 CMOS feature size should be on the order of 22 nm with clock frequencies reaching around ...

There are a number of interesting technologies to keep an eye on in term of how and when they could be adopted for use in SoC design today, some of which include gallium arsenide, GPGPUs, 3D ICs and ...

As the quest grows to manage power in everything from the handheld smart phone to sensors for automotive applications and contactless payment cards, designers are getting hungry for new design ...

As system-on-chip (SoC) designs grow larger, designers must grapple with serious global timing problems, the effect of wire loading and timing delays and the performance hit associated with supporting ...

Asynchronous processors, which function without a global clock, have emerged as a compelling alternative to traditional synchronous architectures. Their design relies on handshake protocols and local ...

Moore’s Law has been the driving force behind computer evolution for more than five decades, fueling the relentless innovation that led to more transistors being added to increasingly smaller ...