Abstract: This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL (SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low Energy ...
Abstract: In this work, we present a continuous-time (CT) pipeline ADC with time-interleaved sub-ADC-DAC path in its first stage. The proposed sub-ADC-DAC path helps in increasing the ADC bandwidth by ...