IEEE

Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect

Abstract: In sub 10 nm nodes, the growing dominance of interconnects in chips poses challenges in designing large-size static random-access memory (SRAM) subarrays. The main issue is the write failure ...
IEEE

Design & Verification of Reconfigurable SRAM Controller with AMBA AXI Protocol Interface for Automobile Application

Abstract: The Static Random Access Memory SRAM Controller with AXI is intended to improve the read/write memory access time and internal connectivity of the semiconductor. Static random-access memory ...