Logic Synthesis flow | RTL Synthesis flow | RTL2GDS | Design Compiler (DC) tutorial
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YouTubeTeam VLSI
Logic Synthesis flow | RTL Synthesis flow | RTL2GDS | Design Compiler (DC) tutorial
Logic Synthesis is performed once the RTL code is simulated and verified. In Logic Synthesis, A RTL code is converted into a gate-level netlist of given standard cell library. Logic Synthesis Flow using DC (Design Compiler of Synopsys) has been explained in this tutorial. In this RTL-to-GDSII flow of video series, there is a total of 10 ...
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